Area-Efficient and Low-Latency On-Chip Communication via a Hybrid Circuit-Packet Switched NoC Router
DOI:
https://doi.org/10.48047/r26jky65Keywords:
Network-on-Chip, Hybrid Router Architecture, Virtual Circuit Switching, Packet Switching, Many-Core SoC, Channel Utilization, Area-Efficient Hardware.Abstract
Efficient Network-on-Chip (NoC) router design is critical in modern many-core System-on-Chip (SoC) architectures, where scalable communication directly dictates overall system performance. Conventional NoC architectures rely on either circuit switching or packet switching. While circuit switching provides predictable paths, it suffers
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. Arulananth, T. S., M. S. M. U. S. Baskar, Udhaya Sankar SM, R. Thiagarajan, Pasupuleti Raja Rajeshwari, Aruru Sai Kumar, and A. Suresh. "Evaluation of low power consumption network on chip routing architecture." Microprocessors and Microsystems 82 (2021): 103809.
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