Design of Improved Ancient Vedic Multiplier Using Verilog
DOI:
https://doi.org/10.48047/ea3kzf79Keywords:
Vedic math, Cross Multiplication, 64x64 Vedic multiplier, Urdhva-Tiryagbhyam sutra”Abstract
Currently, the all-processor core will be consolidated into a singular unit owing to the rising requirement
for high performance in intricate algorithms and multifunctionality. Nevertheless, the CPU demand is substantial.
We should provide copper roses for supportive operations conducted by the primary processor to mitigate it; they will
engage with copper roses. Numerical operations, encompassing joint calculations, multiplications, and digital signal
processing applications, among others. The velocity of coprocessors dictates the processor's performance. Vedic
arithmetic is an ancient kind of calculation characterised by a distinctive methodology of 16 sutras designed to swiftly
derive solutions to various practical problems. Vedic sutras, including Urdva Tirkabhyam, and 64-bit aluminium
architecture are considerations when contemplating. Vedic formulae pertain to multiplication operations. Vedic
formulas significantly assist the enforced arithmetic modules, particularly in instances of delay. Utilising these
mathematical principles, we constructed an aluminium model using Verilog HDL and synthesised it in Xilinx ISE;
we have determined that it exhibits superior performance.
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